This invention generally relates to semiconductor processing methods including photolithographic patterning and more particularly to a method for replicating alignment marks for semiconductor wafer photolithography.
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily, or permanently, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is a preferred electrical isolation technique especially for a semiconductor chip with high integration. STI features can be made using a variety of methods including, for example, the Buried Oxide (BOX) isolation method for shallow trenches. The BOX method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO2), also referred to as an STI oxide which is then etched back or chemically mechanically polished (CMP) to remove the overlying layer of STI oxide to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the substrate, for example, silicon, and are typically between 0.3 and 1.0 microns deep.
Shallow trench isolation features with trenches having submicrometer dimensions are effective in preventing latch-up and punch-through phenomena. Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask, for example silicon nitride, over the targeted trench layer, for example including a pad oxide layer, patterning a photoresist over the hard mask to define a trench feature, anisotropically etching the hard mask to form a patterned hard mask, and thereafter anisotropically etching the trench feature to form the shallow trench isolation feature. Subsequently, the photoresist is removed (e.g., stripped) and the shallow trench isolation feature is back-filled, with a dielectric material, for example a CVD silicon oxide, also referred to as an STI oxide.
In forming the various levels of a multilevel semiconductor device including shallow trench isolation features, semiconductor wafer alignment for positioning the semiconductor wafer for subsequent device feature patterning is critical. In a typical photolithographic patterning procedure, an automated stepper, for example, an ASM Lithography photo system sequentially positions the wafer beneath a photo imaging system for transferring a patterned photo image (mask) of device features to expose a photoresist material overlying the semiconductor wafer surface. As positioning of the process wafer is critical for forming operational semiconductor features, methods for forming alignment marks in the semiconductor wafer surface have evolved to allow the automated stepper to optically sense the alignment marks for proper process wafer positioning.
Several wafer alignment strategies exist for using different patterns and locations to achieve the alignment of a semiconductor wafer to a mask containing an image to be transferred to the wafer. These strategies vary from alignment marks located between shot sites (also known as chip sites) to global alignment marks located in two shot sites at the periphery of the wafer. There are also global strategies in which the alignment marks are located between shot sites in the more peripheral regions of the wafer.
In one approach for global alignment, at least two areas at the wafer periphery are selected, typically located on opposite sides of the wafer diameter and include a series of parallel scribe marks covering area of about 400 micronsxc3x97400 microns referred to as zero-level alignment marks that are etched into the silicon before other processing steps. The global alignment marks are subsequently replicated in each subsequent level of manufacturing the multi-level semiconductor device.
In processes according to the prior art, for example, associated with trench isolation manufacture, a first layer of insulating dielectric layer, often referred to as an STI oxide, for example, silicon oxide, is formed to backfill trenched areas formed in a silicon substrate to form shallow trench isolation features around areas of the device. During the various material depositions and planarization steps the wafer peripheral areas including areas containing alignment marks (alignment mark areas) reflect various global material deposition and planarization steps that are carried out to form semiconductor devices in the active areas of the process wafer. As a result of active area processing steps the alignment mark areas include a layer of the STI oxide.
To preserve replication of the alignment marks for use in subsequent photolithographic patterning steps, in one approach, an anisotropic etching process is carried out on the STI oxide to form a window area to surround the alignment mark areas and to expose the underlying alignment marks with the window area having a depth greater than a subsequent STI oxide CMP polishing depth. A CMP step is subsequently carried out to planarize the STI oxide having a CMP polishing depth less than the previously formed window areas thereby preserving the alignment marks. Following the STI oxide CMP step a layer of polysilicon is conformally deposited thereby replicating the alignment marks. Following deposition and patterning steps performed on the polysilicon layer an insulating dielectric layer also often referred to as an interlayer dielectric (ILD) is conformally deposited and planarized according to a CMP process. Subsequently a metal layer, for example copper, is deposited and subsequently planarized according to a CMP process.
One problem according to prior art methods of replicating alignment marks, is that the window areas formed to surround the alignment marks necessarily having a step height or depth sufficient to survive a subsequent STI oxide CMP step, causes a recessed area to remain in the ILD layer overlying the alignment mark area following deposition and planarization of the ILD layer. The formation of the recessed area is due to the conformal nature of subsequently deposited layers and the step height of the window area formed over the alignment mark area. As a result, in depositing and planarizing the subsequent metal layer, the recessed areas including over the alignment mark area in the ILD layer tend to accumulate residual metal, for example copper, following a CMP step. In subsequent processing steps, for example to form metal interconnects such as damascene features in overlying insulating dielectric layers, the alignment process for photolithographically patterning such structures is likely to fail as the metallic residue interferes with overlying oxide. As a result photolithographic patterning steps are compromised.
Therefore, there is a need in the semiconductor processing art to develop an improved method for replicating alignment marks such that residual metal forming over alignment marks is avoided.
It is therefore an object of the invention to provide an improved method for replicating alignment marks such that residual metal forming over alignment marks is avoided while overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for avoiding a step height over an alignment mark area.
In a first embodiment the method includes providing at least one alignment mark area disposed at a semiconductor wafer process surface periphery said alignment mark area having alignment marks anisotropically etched into the semiconductor wafer process surface; depositing a first insulating dielectric layer over an active area of the semiconductor wafer process surface to include covering the at least one alignment mark area; planarizing the first insulating dielectric layer; depositing a polysilicon layer over the active area of the semiconductor wafer process surface to include covering the at least one alignment mark area; and, anisotropically etching the polysilicon layer through a thickness over the at least one alignment mark area to form an opening extending no further than about the first insulating dielectric layer to minimize a step height.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.